1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of fabricating the same. More specifically, the present invention is directed to a nonvolatile memory device having a shallow trench isolation (STI) structure and a method of fabricating the same.
2. Description of the Related Art
As the trend in the field of semiconductor devices continues toward higher density integration, the demand and need for decreasing the fine linewidth of a gate and the width of a device isolation layer also grows. Shallow trench isolation (STI) technology has become more widely adopted and used than local oxidation of silicon (LOCOS) technology because a narrower and deeper device isolation layer can be formed. However, STI technology requires the use of a diffusion barrier layer to prevent deterioration of an interface between a semiconductor substrate and a device isolation layer, and a groove is formed between the device isolation layer and an active region. This results in generation of a leakage current and deterioration of a gate oxide layer. In order to overcome such problems, a self-aligned trench technology has recently been employed in which a gate oxide layer is formed during formation of a trench isolation layer to simplify the process. Since the trench isolation layer is formed after formation of the gate oxide layer and ion implantation, the conventional problems associated with STI technology can be solved. Unfortunately, in spite of the foregoing advantages, the self-aligned trench technology suffers from several problems that occur while fabricating semiconductor devices.
FIG. 1 illustrates a top, plan view for explaining a general nonvolatile memory, in which region “a” represents a cell array region and region “b” represents a peripheral circuit region.
Referring now to FIG. 1, device isolation layers 108 (208) are disposed over a semiconductor substrate in the cell array region “a” along one direction. A plurality of control gate electrodes 112 is located across an active region 106 between the device isolation layers 108 (208). A floating gate “F” is disposed between the control gate electrode 112 and the active region 106. A transistor in the peripheral circuit region “b” includes a gate electrode 114 crossing an active region 107 defined by the device isolation layers 108 (208).
FIGS. 2 through 4 illustrate flow diagrams for explaining problems of a conventional memory device, which are taken along a line I-I′ of FIG. 1.
Referring now to FIG. 2, a gate oxide layer 102, a lower conductive layer 104, and a hard mask layer 105 are sequentially formed on a semiconductor substrate 100 with a cell array region “a” and a peripheral circuit region “b”. Thickness of the gate oxide layer may be different in the cell array region and the peripheral circuit region. The hard mask layer 105, the lower conductive layer 104, and the gate oxide layer 102 are sequentially patterned to form a lower conductive pattern 104 and a hard mask pattern 105 that are sequentially stacked in the cell array region “a” and the peripheral circuit region “b”. The cell gate oxide layer (tunnel oxide layer) 102 is disposed between the lower conductive pattern 104 and the semiconductor substrate 100 in the cell array region “a”. Also, the gate oxide layer 102 is disposed between the lower conductive layer pattern 104 and the semiconductor substrate 100 in the peripheral circuit region “b”. Using the hard mask pattern 105 as an etch mask, the semiconductor substrate 100 is etched to form a trench area “T” and to define first and second active regions 106 and 107 in the regions “a” and “b”, respectively.
Referring now to FIG. 3, a device isolation layer 108 is formed in the trench area “T” by first forming an insulating layer to fill the trench area “T”. The insulting layer is then etched to expose the hard mask pattern 105 using a chemical mechanical polishing (CMP) technique and thereafter recessed to form the device isolation layer 108.
Prior to the formation of the insulating layer, defects in the semiconductor substrate that formed during formation of the trench area “T” are recovered by a process whereby a thermal oxide layer is formed. In this process, a sidewall of the lower conductive pattern 104 is also oxidized, and an edge of the lower conductive layer pattern 104 is bent by a tensile stress applied thereto. Thus, the lower conductive pattern 104 has a structure where the width at a lower portion is larger than the width at an upper portion. Also, the device isolation layer 108 protruding into the semiconductor substrate 100 has a structure where the width at an upper portion is larger than the width at a lower portion.
Referring now to FIG. 4, hard mask patterns 105 on the first and second active regions 106 and 107 are removed. Generally, the hard mask layer is made of silicon nitride, and the hard mask patterns 105 may be etched by wet etch using the solution of phosphoric acid. An upper conductive layer is formed over the entire surface of the semiconductor substrate from which the hard mask patterns 105 have been removed. The upper conductive layer is then patterned to form a floating gate pattern, which comprises the upper and lower conducive layer 104, on the first active region 106. A gate interlayer dielectric film and a control gate conductive layer are formed to cover the cell array region “a”. In the cell array region “a”, the control gate conductive layer, the gate interlayer dielectric film, and the floating gate pattern are sequentially patterned to form a control gate electrode (112 of FIG. 1) crossing the first active region 106 and a floating gate (“F” of FIG. 1) disposed between the gate electrode (112 of FIG. 1) and the first active region 106. The gate electrode 114 consists of a lower gate electrode 104 and an upper gate electrode 111. In the peripheral circuit region “b”, the upper conductive layer and lower conductive layer 104 are sequentially patterned to form a gate electrode 114 crossing the second active region.
In the prior art, an upper width of the device isolation layer 108 protruding into the semiconductor substrate is larger than a lower width thereof. This causes a stringer 113, which remains along a boundary of the first and second active regions 106 and 107 in a process for forming a control gate (not shown) in the cell array region “a” and a gate electrode 114 in the peripheral circuit region “b”. Since the stringer electrically connects adjacent floating gates “F” (see FIG. 1) in the cell array region “a” to each other, it is difficult to program one cell transistor independently.